1. Field of the Invention
The present invention relates to a pipeline operation processor having a pipeline processing function and to a control system comprising a shared memory which stores a program to be executed by the pipeline operation processor and operation data. More particularly, the present invention relates to a pipeline operation processor which reduces deterioration of processing efficiency in the case where another processor sharing the shared memory accesses the shared memory and to a control system comprising the pipeline operation processor.
2. Description of the Related Art
In recent years, a pipeline operation processor having a pipeline processing function has been employed to fulfill a requirement for high-speed processing of a control system.
Conventionally, a system having the configuration shown in FIG. 11 is utilized in a control system for a plant or the like. The control system includes a pipeline operation processor 12, which processes data from an external input-output (I/O) device such as a process sensor or an actuator at high speed, general-purpose processors 11a and 11b, which manage the pipeline operation processor 12 or execute different processing, an external input-output (I/O) memory 13, which functions as an interface for transferring input and output data of the external I/O device, and an operation memory 14, which stores a control program 14a to be executed by the pipeline operation processor 12 and is shared by the pipeline operation processor 12 and the general purpose processors 11a and 11b. 
A pipeline processing unit 12b includes an instruction fetch unit 12b1, an instruction decoding unit 12b2, an instruction execution and address generation unit 12b3, memory access units 12b4 and 12b5, and a writing unit 12b6. The pipeline processing unit 12b further includes a bypass control circuit (not shown), which controls data paths between these units, an external I/O memory access unit 12b8, an operation memory access unit 12b9, and a pipeline bus 12b7, which connects the units of the pipeline processing unit 12b. 
The pipeline processing unit 12b divides an instruction into 6 basic stages corresponding respectively to the instruction fetch unit (IF) 12b1, the instruction decoding unit (ID) 12b2, the instruction execution unit (MAR) 12b3, the memory access units (MADR, MDR) 12b4 and 12b5, and the writing unit (WR) 12b6. Thus, instructions are processed in parallel to improve throughput of the processing. When a change occurs in operation of a scheduled stage, executions of stages are suspended (or stalled) partway, restarted from the beginning, or the instruction sequence needs to be changed.
Data hazard resulting from a load instruction is one example of a cause of such a change. A method to predict an address of the load instruction for preventing a pipeline stall caused by the data hazard is disclosed, for example, in Japanese Patent No. 3435267.
The principle of pipeline processing and a technique to solve various hazards in execution of pipeline processing are disclosed, for example, in the chapter 6, pages 23-70 of “Computer Architecture and Design (Vol. 2)” written by John L. Hennessy and David A. Patterson, published by Nikkei Business Publications Inc. on Jun. 26, 1996.
FIGS. 12A and 12B show typical operations of pipeline processing by the control system of the plant or the like, which utilizes the conventional pipeline operation processor shown in FIG. 11.
For example, each of instructions A to F is processed in 6 stages as shown in FIG. 12A, and operation of each stage is synchronized with a clock signal. Executions of the respective instructions are shifted by one stage.
Conventionally, when the shared memory is accessed from the general-purpose processor 11a via a memory access unit 12a, for example, in the case where instruction B is being processed in a stage of the writing unit WR, the memory access unit 12a sends a signal to stop operations of all the stages of the pipeline processing unit 12b, as shown in FIG. 12B, and accesses the operation memory 14 via the operation memory access unit 12b9 within the period of stopping.
In such a case, the period of stopping interrupts memory cycle processing of instructions B to F, which are in operation; therefore, operation phases of stages surrounded by dotted lines in FIG. 12B are changed from an operation phase of a synchronous memory and may not be executed normally.
Therefore, instructions B to F need to be executed again after stopping the pipeline processing is cancelled as shown in FIG. 12B. Thus, the processing efficiency of the pipeline operation processor 12 is considerably reduced.
That is, performance of the processing using the conventional pipeline operation processor may deteriorate due to a disadvantage that a stage of the pipeline processing running partway is restarted from the beginning when a change occurs in a scheduled operation.